The effective work function (WF) of a gate stack sets the threshold voltages (Vt) of fully depleted, thin-body complementary metal oxide semiconductor (CMOS) devices such as metal oxide semiconductor field effect transistors (MOSFETs). The Vt of a CMOS device is the voltage, applied to the gate, that is necessary to open a conductive channel between source and drain of the device. For high-performance (HP) CMOS Fully Depleted (FD) devices, a desirable effective WF is +/−0.2 eV away from mid-band-gap. For low-power (LP) CMOS FD devices, a mid-band-gap effective WF alone is enough. One method of modulating the effective WF of a CMOS device is ion implantation. For example, Fluorine (F) implants can modulate the effective WF through the creation of negative charge states at the Si and gate dielectric interfaces.
System-on-Chip (SoC) applications often include both LP CMOS devices and HP CMOS devices which themselves include multiple semiconductor types of CMOS devices such as P-type CMOS (PMOS) devices and N-type CMOS (NMOS) devices. The LP CMOS devices and HP CMOS devices require gate stacks with different effective WF and the NMOS devices and PMOS devices may require different effective WF. As such, SoC applications require the integration of multiple effective WF gate stacks on the same chip. However, individually forming each gate for the different CMOS devices requires additional processing steps.
As such, there is a need for methods for forming semiconductor devices with different effective WF without adversely affecting other devices on the same chip. Additionally, the implantations of ions such as F can modulate the effective WF of some devices and adversely affect other devices. As such, there is a need for methods for forming semiconductor devices with different effective WF without adversely affecting other devices on the same chip.